The inventive concept relates to memory modules within data processing apparatuses. More particularly, the inventive concept relates to a memory board structure in which a plurality of memory modules is connected to module sockets on a main board.
Various integrated circuit devices, (e.g., memory devices, control devices and related logic devices) are operationally and functionally grouped to implement various data processing apparatuses, such as personal computers, portable computers, PDAs, servers, workstations, etc.
The principle data storage unit (or “main memory”) within many data processing apparatuses is implemented with dynamic random access memories (DRAMs). The DRAM is a type of volatile memory wherein a transistor is used in each memory cell to access data in the form of electrical charge placed on a corresponding storage capacitor.
As typically implemented to form a main memory, a collection of DRAMs is operationally and functionally grouped on a memory module. The term “memory module” is well understood in the art and generally refers to a plurality of individual memory devices (i.e., separate integrated circuits) grouped to operate in response to various functional commands. In one common configuration, a memory module assembles a plurality of integrated circuit devices, principally including memory devices, on a printed circuit board (PCB). Each integrated circuit device on the memory module is electrically connected to circuitry on a corresponding main PCB (or “main board”, sometimes referred to as the motherboard) via a plurality of connection pins (or “taps”).
Conventional examples of memory modules including a plurality of memory devices mounted on a PCB include the single in-line memory module (SIMM) and the dual in-line memory module (DIMM). The SIMM mounts memory devices on only one principal surface (or “one side”) of a PCB. The DIMM mounts memory devices on both sides of a PCB. In recent years, the DIMM has been more generally used as the memory module.
As operatively assembled, the DIMM is inserted into a connector (or module socket) secured to the main board. In certain data processing apparatuses, a plurality of memory modules may be commonly connected to a memory controller and/or central processing unit (CPU) via one or more buses. This configuration allows a great number of DRAMs to be functionally assembled into a large main memory.
Conventional DIMMs include the fully buffered dual in-line memory module (FBDIMM) and the registered dual in-line memory module (RDIMM). Certain data processing apparatuses, such as servers, process very large quantities of data. Accordingly, RDIMMs are widely used as constituent memory modules within servers. The FBDIMM is generally used where a relatively high-speed data packet is provided in a data processing apparatus (e.g., from a microprocessor) to a constituent memory system. The data packet must be converted into a compatible memory command and properly synchronized before data can be accessed.
There are many data processing apparatuses that use this type of approach. Consider for example, the conventionally understood stub series terminated transceiver logic (SSTL) which is used as a small-amplitude interface within certain memory systems. (See, e.g., Konishi et al., “Interface Technologies for Memories and ASICs-Review and Future Direction”, Vol. E82-C, No. 3.) In general, a memory system including the SSTL includes a memory controller, a signal line, a connector, and a memory module—all collectively mounted on a main board.
Within this type of memory system, the memory module includes “M” memory devices (M being a natural number equal to or greater than 2) mounted on both surfaces of the module substrate. Data terminals for the M memory devices are connected to each module data terminal. An access control data terminal, (e.g., an address terminal) for each memory device is connected to a corresponding module access control terminal. The signal line connects at one end a signal terminal of the memory controller and at the other end a terminal having a predetermined voltage. A plurality of memory modules is connected in parallel to the signal line via connectors.
In a case where the number of data terminals in a memory device is “N” (N being a natural number equal to or greater than 2) and the number of memory devices mounted on one side of each memory module is M, the memory system will have (M×N) data signal lines. During each data access operation (e.g., a read or write operation) M memory devices mounted on a plurality of memory modules may be selected using a device selection signal generated by the memory controller. In this configuration, one end of each signal line may be connected to a termination voltage through a termination resistor.
Various “module lines” (e.g., command, address, and/or data signal lines) that connect to the module terminal of the memory module and the terminals of the memory devices may include wiring lines branched from signal line(s) on the main board through corresponding connectors. These module lines may further have stub resistors provided therein. The stub resistors serve as matching loads that reduce signal reflections on the module lines.
Characteristic impedance mismatching generally occurs at a branch point of a module line. Therefore, the stub resistor is needed to reduce the characteristic impedance mismatching. However, as the resistance value of the stub resistor increases, a corresponding voltage drop increases. As a result, the attenuation of signal voltages (e.g., address and data signals) can occur and errors may arise during data access operations.
On the other hand, when the resistance value of the stub resistor is reduced in order to avoid signal voltage attenuation, signal reflections may occur and signal voltage waveforms may become distorted, and such distortions may also result in errors. And as the data access speed of contemporary memory systems increases, the frequency of signal waveforms also increases and the risk of significant distortion rises. Further, as the length of module lines increases the risk of signal waveform distortion also rises. In memory systems using SSTL, module lines traversing the memory module and the memory system generally include signal line branching. Such branching, as noted above, also increases the risk of errors occurring during data access operations due to signal reflections (really, just another form of signal line noise or interference). Thus, module line branching has been one factor limiting further increases in the operating speed of memory systems.
The conventional synchronous dynamic random access memory (SDRAM) synchronously provides in simultaneous sequence (1) input of a column address, (2) reading of data, and (3) output of data (i.e., the SDRAM provides a three-stage data pipe line). In contrast, the DRAM processes data only during a period between receipt of a column address and data output. Since the SDRAM synchronously operates through a three-stage data pipe line at least three (3) clocks are required to initially output data, but a single clock is required after the start-up period. Hence, it is possible to access data from a SRAM at relatively high speed.
In this context, the double data rate (DDR) registered DIMM processes data synchronously with both the rising and falling edges of a clock signal, unlike the SDRAM that processes data in synchronization with the rising edge of the clock signal.
In a general DIMM, stub resistors are provided on the substrate (or “board”) of the memory module. Daisy chain or T-branch connection may also be used for module lines traversing the memory module board. However, it is preferable to use the T-branch structure in order to increase a memory access operation speed.
In order to reduce manufacturing cost and overall size of memory modules, it is necessary to address the problems associated with stub resistors provided on memory module boards. In addition, it is necessary to provide a memory module capable of operating at high-speed within various data processing apparatuses.